1. Field of the Invention
The present invention relates generally to compositions for chemical-mechanical planarization, and more particularly to compositions for chemical-mechanical planarization of substrates (“noble-metal-featured substrates”) having surface features comprising noble metals, noble metal alloys, noble metal oxides, and combinations thereof, associated methods, and substrates produced by such methods.
2. Description of Related Art
Chemical-Mechanical Planarization (also referred to as Chemical-Mechanical Polishing), or CMP, is commonly used in the manufacture of semiconductor devices and denotes the process of removing material and forming a substantially planar surface before additional layers are deposited and/or additional patterning of the layers occurs. CMP processes have been extensively studied for use in semiconductor fabrication and constitute integral steps in many practical production environments. However, CMP of metals has been studied most extensively in connection with metals such as tungsten, copper, aluminum, tantalum, among others, as well as oxides, nitrides and alloys thereof See, for example, Chemical Mechanical Planarization of Microelectronic Materials, by J. M. Steigerwald, S. P. Murarka and R. J. Gutmann (John Wiley & Sons 1997), especially Chapters 5-8. In contrast, CMP of noble metals, including alloys and oxides thereof, is much less well studied. The term “noble metals” typically refers to less reactive metals such as gold, silver, platinum, iridium and other elements typically found in or near Group VIII of the periodic table.
Interest in noble metals, and the alloys and oxides thereof, is increasing as such materials are useful as electrode and barrier materials in the fabrication of some electronic devices such as Gigabit (109 bit) DRAMs (dynamic random access memories) and FeRAMs (ferroelectric random access memories). Worldwide efforts are underway to commercialize high dielectric constant and ferroelectric thin films for use in capacitive elements as would be applied, for example, in advanced DRAMs and FeRAMs. High dielectric constant materials such as BaSrTiO3 (BST) can be used for forming capacitor dielectrics in submicron integrated circuits (e. g. in DRAM storage capacitors, coupling capacitors in general circuits, among other uses). Additionally, ferroelectric materials such as PbZrTiO3 (PZT) and SrBi2Ti2O9 that can store charge for extended periods of time can be employed in the fabrication of non-volatile FeRAM memory elements. The chemical properties of these (and other) high dielectric constant and ferroelectric materials typically require that they be used in conjunction with noble metals, noble metal oxides and/or noble metal alloys (including Pt, Ir, IrO2, among others). Examples of the use of high dielectric constant and/or ferroelectric materials in semiconductor fabrication and in conjunction with noble metals, noble metal alloys, and noble metal oxides, can be found in the following U.S. Pat. Nos. 5,318,927; 5,527,423; 5,976,928; 6,169,305, and references cited therein.
Conventional patterning of noble metals, noble metal alloys, and noble metal oxides includes the use of dry etching processes. However, dry etching has several disadvantages including unfavorable taper angle, fence formation, and a tendency to produce residual particles leading to contamination. Some of these disadvantages of conventional dry etching are due to the predominantly physical rather than chemical mechanism for material removal. Physical removal of material is prone to the formation of unwanted structures at the edges of the structures, such as electrodes, being etched.